Science Blog about Microelectronics of Fraunhofer IZM

Tag - Wafer Level Packaging

Wafer Level Packaging is a synonym for the whole technology spectrum enabling direct chip attachment on PWB or other substrates by Flip Chip Interconnection.

In contrast to pure bumping processes additional thin film wiring layers are required featuring a higher level of integration by embedding active or passive devices onto the chip.

The technology is feasible for any kind of CMOS wafers but also for III/V or even sensors.