M. Juergen Wolf received his M.S. degree in Electrical Engineering from the Technical University of Chemnitz before starting out in his professional career as a technology supervisor in the microelectronic industry. He joined the Fraunhofer Institute for Reliability and Microintegration IZM Berlin in 1994, where he has held a range of positions, including as Group & Project Manager in the field of wafer level packaging and system-in-package (SiP) and as Assistant to the Director. Since 2011, he has been in charge of Fraunhofer IZM-ASSID - “All Silicon System Integration Dresden”, with its 300 mm process line for 3D wafer-level system integration, and the Wafer-Level System Integration department. M. Juergen Wolf leads a number of research projects on the national, European, and international level. He is a member of IEEE and SMTA and a longstanding member and European representative in several international packaging roadmap groups, e.g. the Heterogeneous Integration Roadmap (HIR) and its predecessor TWG Assembly & Packaging of the International Roadmap of Semiconductors (ITRS). In 2016, M. J. Wolf was also chosen to join the advisory board of 3D InCites. He has authored and co-authored numerous scientific papers and reports on microelectronic packaging and 3D integration and holds a number of patents.
Fraunhofer IZM-ASSID (All Silicon System Integration Dresden) is a dedicated business unit of Fraunhofer IZM located in Dresden/Moritzburg, Saxony. With its 300 mm wafer-level packaging process line, its mission is to develop custom system integration technologies for industrial partners, with…
